1. Field of the Invention
This invention relates to semiconductor integrated circuit devices, and specifically to integrated BICMOS vertical transistors, and a method for making the same. More specifically, the invention relates to a vertical PNP transistor, and a set of complementary vertical NPN and PNP transistors in a downward mode or collector down configuration.
2. Description of Related Art
Integrated circuit technologies are predominantly of the NPN type, generally without an available high-speed complementary PNP device. Circuit designers would certainly benefit from the inclusion of a complementary PNP device; however, in the development of a complementary PNP transistor, cost becomes a dominant factor. It has been a continuing technological challenge to integrate vertical PNP devices into a high performance NPN process without significantly degrading the performance of the NPN device. A problem for complementary transistors using the same layers and process fabrication steps is that the mode of operation of the two devices is different, i.e., one operates in an upward direction and the other operates in a downward direction. This is due to the order of the material layers deposited and implanted with dopants for the emitter, base and collector regions of each transistor.
One prior art example of a complementary transistor structure is found in U.S. Pat. No. 4,997,776 issued to Harame, et al., on Mar. 5, 1991 entitled, “COMPLEMENTARY BIPOLAR TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURE.” The Harame structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. The intrinsic vertical profiles for both the NPN and PNP transistors are formed by depositing a first layer of p-doped silicon and a second layer of n-doped silicon. These layers form the intrinsic base and collector regions for both the NPN and PNP transistors. The first layer forms the base and the second layer the collector for an NPN transistor operating in an upward direction. Simultaneously, the second layer forms the base and the first layer forms the collector for a PNP transistor operating in a downward direction. Importantly, Harame has two SiGe layers, one n-type and one p-type for forming the complementary pair of upward and downward transistors. In the present invention, only one SiGe layer is taught for two downward complementary transistors.
In U.S. Pat. No. 5,930,635 issued to Bashir, et al., on Jul. 27, 1999 entitled, “COMPLEMENTARY SI/SIGE HETEROJUNCTION BIPOLAR TECHNOLOGY,” bipolar transistors are formed on a common substrate. The transistors are vertical NPN and PNP transistors, which have identical structure and modes of operation with both devices operating in the downward direction. However, the emitter region of the PNP transistor is not the same layer as the base region of the NPN transistor.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a complementary pair of transistors that are vertically aligned and operate in a single direction.
It is another object of the present invention to provide vertical transistors that share a single layer to form the extrinsic base of an NPN transistor and an emitter of a PNP transistor.
A further object of the invention is to provide a vertically aligned PNP transistor that shares its emitter layer with the base layer of a vertically aligned NPN transistor, and utilizes an epitaxial growth process to form a PNP base/collector region and NPN base/collector region where the PNP emitter layer is also used as the NPN base layer.
It is yet another object of the present invention to provide a method of making vertical transistors where the base layer for the NPN and PNP transistors are in the same SiGe LTE layer.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.